1. Field of the Invention
The present invention relates to a Gray code counter.
2. Description of the Prior Art
Some solid-state image sensors adopt a scanning circuit of a decoder type. A decoder-type scanning circuit is provided with a counter, and scans the address that coincides with the value output from the counter. By making this counter perform the desired counting operation, it is possible to achieve image sensing.
Conventionally, such a decoder-type scanning circuit employs a binary counter. However, in a binary counter, an increment or decrement by one of its decimal count sometimes causes simultaneous change in a plurality of bits. For example, in a 5-bit binary counter, when its decimal count changes from “0” to “1,” as FIG. 2 shows, the binary code changes from (00000) to (00001), causing change only in one bit. By contrast, when the decimal count changes from “15” to “16,” as FIG. 2 shows, the binary code changes from (01111) to (10000), causing change in five bits simultaneously. The greater the number of bits in which such change takes place simultaneously, the more power current flows through the system in which the counter is provided, causing electric noise. This may lead to interference between signals within the system, and thus to malfunctioning of the system.
To reduce such electric noise, it is customary to use a Gray code counter. FIG. 22 shows a typical circuit configuration of a 5-bit Gray code counter.
The Q output terminal of a flip-flop FF6 is connected through a buffer BUF1 to the C input terminal of a flip-flop FF1. The XQ output terminal of the flip-flop FF6 is connected to the first input terminal of each of NAND circuits NA1 to NA4.
The second input terminal of the NAND circuit NA1 is connected to the Q output terminal of the flip-flop FF1. The output terminal of the NAND circuit NA1 is connected through an inverter circuit INV1 to the C input terminal of a flip-flop FF2.
The second input terminal of the NAND circuit NA2 is connected to the XQ output terminal of the flip-flop FF1, and the third input terminal of the NAND circuit NA2 is connected to the Q output terminal of the flip-flop FF2. The output terminal of the NAND circuit NA2 is connected through an inverter circuit INV2 to the C input terminal of a flip-flop FF3.
The second input terminal of the NAND circuit NA3 is connected to the XQ output terminal of the flip-flop FF1, the third input terminal of the NAND circuit NA3 is connected to the XQ output terminal of the flip-flop FF2, and the fourth input terminal of the NAND circuit NA3 is connected to the Q output terminal of the flip-flop FF3. The output terminal of the NAND circuit NA3 is connected through an inverter circuit INV3 to the C input terminal of a flip-flop FF4.
The second input terminal of the NAND circuit NA4 is connected to the XQ output terminal of the flip-flop FF1, the third input terminal of the NAND circuit NA4 is connected to the XQ output terminal of the flip-flop FF2, the fourth input terminal of the NAND circuit NA4 is connected to the XQ output terminal of the flip-flop FF3, and the fifth input terminal of the NAND circuit NA4 is connected to the Q output terminal of the flip-flop FF4. The output terminal of the NAND circuit NA4 is connected through an inverter circuit INV4 to the C input terminal of a flip-flop FF5.
Moreover, in each of the flip-flops FF1 to FF6, the XQ output terminal and the D input terminal are connected together. Thus, in each of the flip-flops FF1 to FF6, every time the clock signal fed to their C input terminal rises, the output signal output from their Q output terminal is inverted.
The buffer BUF1, the NAND circuits NA1 to NA4, and the inverter circuits INV1 to INV4 together constitute a clock generating circuit 21, which functions as a circuit that generates clocks that determine the timing with which the individual outputs of the Gray code counter 2 are inverted.
Next, the operation of this Gray code counter 2 will be described with reference to FIGS. 22 and 23. Here, it is assumed that the set signals SETQ0 to SETQ4 and SETNCK fed respectively to the XS terminals of the flip-flops FF1 to FF6 are kept at “1” all the time, and that the reset signals RESETQ0 to RESETQ4 and RESETNCK fed respectively to the XR terminals of the flip-flops FF1 to FF6 are initially set at “0” and are then turned to “1.”
The flip-flop FF6 receives a reference clock signal CK, produces a ½ clock signal NCK by dividing the reference clock signal CK by a factor of 2, and feeds the ½ clock signal NCK and the inverted version NCKX thereof to the clock generating circuit 21 in the following stage.
The clock generating circuit 21 produces a clock signal Q0CKN that is identical with the ½ clock signal NCK. The flip-flop FF1 receives the clock signal Q0CKN from the clock generating circuit 21, and therefore outputs an output signal Q0p that is inverted every time the ½ clock signal NCK rises and the inverted version Q0X of that output signal Q0p. 
The clock generating circuit 21 also produces a clock signal Q1CKN that rises when the ½ clock signal NCK falls while the output signal Q0p is at “1.” The flip-flop FF2 receives the clock signal Q1CKN from the clock generating circuit 21, and therefore outputs an output signal Q1p that is inverted every time the clock signal Q1CKN rises and the inverted version Q1X of that output signal Q1p. 
The clock generating circuit 21 also produces a clock signal Q2CKN that rises when the ½ clock signal NCK falls while the output signal Q0p is at “0” and the output signal Q1p is at “1.” The flip-flop FF3 receives the clock signal Q2CKN from the clock generating circuit 21, and therefore outputs an output signal Q2p that is inverted every time the clock signal Q2CKN rises and the inverted version Q2X of that output signal Q2p. 
The clock generating circuit 21 also produces a clock signal Q3CKN that rises when the ½ clock signal NCK falls while the output signal Q0p is at “0,” the output signal Q1p is at “0,” and the output signal Q2p is at “1.” The flip-flop FF4 receives the clock signal Q3CKN from the clock generating circuit 21, and therefore outputs an output signal Q3p that is inverted every time the clock signal Q3CKN rises and the inverted version Q3X of that output signal Q3p. 
The clock generating circuit 21 also produces a clock signal Q4CKN that rises when the ½ clock signal NCK falls while the output signal Q0p is at “0,” the output signal Q1p is at “0,” the output signal Q2p is at “0,” and the output signal Q3p is at “1.” The flip-flop FF5 receives the clock signal Q4CKN from the clock generating circuit 21, and therefore outputs an output signal Q4p that is inverted every time the clock signal Q4CKN rises and the inverted version Q4X of that output signal Q4p. 
If it is assumed that the output signal Q0p is the output for the zeroth bit, i.e. the lowest bit, the output signal Q1p is the output for the first bit, the output signal Q2p is the output for the second bit, the output signal Q3p is the output for the third bit, and the output signal Q4p is the output for the fourth bit, i.e. the highest bit, then the Gray code counter 2 outputs the Gray code shown in FIG. 2 according to the decimal count of the clock signal CK.
In a Gray code, any two consecutive decimal counts are represented by codewords that differ only in one bit and that are identical in the other bits. That is, between any two consecutive decimal counts, change takes place only in one bit. Accordingly, with a Gray code, change in bits is accompanied by less current, and thus less noise, than with a binary code.
On the other hand, in a solid-state image sensor, it is sometimes necessary to make a counter perform interlaced counting, i.e. to make a decoder-type scanning circuit perform interlaced scanning.
For example, by switching between interlaced scanning and ordinary (non-interlaced) scanning, it is possible to furnish a solid-state image sensor with an electronic zoom function. Specifically, for ordinary image sensing (without electronic zooming), interlaced scanning is performed, and, for image sensing using electronic zooming, ordinary scanning is performed. Now, how this is achieved will be described, taking up as an example a case in which are used a solid-state image sensor of which the image sensing area has 200 addresses (pixels) horizontally and 200 addresses (pixels) vertically and a display device of which the display area has 100 pixels horizontally and 100 pixels vertically.
In ordinary image sensing (without electronic zooming), the solid-state image sensor scans every second address, like 0, 2, 4, . . . , 196, and 198, both horizontally and vertically, so that image data is acquired at 10,000 (100×100) pixels and an image based thereon is displayed on the display device. When electronic zooming is used, the solid-state image sensor scans every address, like 0, 1, 2, . . . , 98, and 99, both horizontally and vertically, so that image data is acquired at 10,000 (100×100) pixels and an image based thereon is displayed on the display device. In this case, where electronic zooming is used, the image displayed is the fourfold magnified (zoomed in) version of the upper left-hand quarter of the image obtained in ordinary image sensing.
Moreover, in a solid-state image sensor, it is sometimes necessary to take both still and moving pictures. With a moving picture, it is often difficult to scan all the addresses because of restrictions associated with the processing frequency. By contrast, with a still picture, there are no such restrictions associated with the processing frequency, and therefore it is desirable to scan all the addresses to obtain the highest possible resolution. That is, it is advisable to scan all the addresses with a still picture and scan the addresses in an interlaced manner with a moving picture.
However, a Gray code is more difficult to handle in operation (in particular, addition) than a binary code, and the code itself is complex. This makes it difficult to design the logic of a Gray code counter that can be used in interlaced counting. For this reason, where interlaced counting as described above is necessary, it is customary to use a binary counter. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the number of counts skipped at a time when interlaced counting is performed. For example, in a case where interlaced counting is performed with 9 counts skipped at a time, when the count changes from “0” to “10,” the Gray code changes from (00000) to (01111), with four bits changing simultaneously. This spoils the advantage of a Gray code of reducing the number of simultaneously changing bits.
Furthermore, in a solid-state image sensor, to permit a portion of the screen to be cut out, it is necessary to use a decoder-type scanning circuit that can scan from a specified address to a specified address, i.e. that permits random access. For example, in a solid-state image sensor having 200 addresses horizontally, by scanning only addresses 100 to 149, it is possible to cut out the image corresponding to addresses 100 to 149 without scanning the image corresponding to addresses 1 to 99 and 150 to 200. To achieve this, it is essential to use a counter that permits the counts at which to start and stop counting to be specified freely.